Expanding into the third dimension enables chip manufacturers to continue shrinking transistors to boost speed without adding power leaks. However, chip stacking is limited by wiring-related problems. Today's interconnects do not run through the silicon itself but go millimeters around it, impeding speedy signaling and increasing power consumption along the way. 2-D (horizontal) real estate is also valuable. Even the thinnest interconnects must still be packed along the edges of a chip, imposing strict limits on how many input/output connections the chip can handle. Consequently, going vertical (3-D) by connecting one chip to another with lines that go straight through the silicon—commonly known as through-silicon vias (TSVs)—offers the numerous potential benefits. In particular, more connections can be packed side by side using much slimmer wires. Going through chips instead of around the side also reduces the length of interconnects from millimeters to microns or even less—as thin as individual wafers can be produced. It has been estimated that the switch to vertical interconnects may reduce power consumption in half, increase bandwidth by a factor of eight, and shrink memory stacks by some 35 percent.
As several hundreds of thousands of TSVs in a single package provide power/ground, clock, functional signals, as well as test access to logic blocks of different layers of the device, they become not only the key components of 3-D ICs but also make up a crucial test infrastructure. In order to form TSVs, one has to etch deep, narrow holes into a silicon wafer and then fill them with a nearly flawless layer of insulating material and then copper. But as a wafer heats up, copper expands at more than five times the rate that silicon does, exerting stress that can crack the wafer and render it useless. Because of such imperfect etching, ragged wafer surface, and potential wafer misalignments, certain TSVs in one wafer after thinning and polishing might not be completely exposed or aligned with their counterparts on the other wafer. Since the bonding quality of TSVs depends on the winding level of the thinned wafer as well as the surface roughness and cleanness of silicon dies, defective TSVs tend to occur in clusters, though even a single TSV defect between any two layers can void the entire chip stack, reducing the overall yield.
Numerous novel schemes for testing TSV-based interconnects have been proposed. Among them, the ring oscillator-based scheme is a promising technique. Using the technique, TSVs can be tested before and after dies are stacked together (pre-bond testing and post-bond testing). FIGS. 1A and 1B illustrate examples of pre-bond testing and post-bond testing, respectively. In the example of pre-bond testing, a ring oscillator is configured for each TSV. The ring oscillator oscillates when the signal EnableRO 110 is set to be 1. The signal S 120 can be used to adjust the drive strength of the inventor 130. During a test, oscillation periods are measured under two configurations: (1) S=0 and (2) S=1. In the example of post-bond testing, a ring oscillator is configured for each pair of TSVs. Similar to pre-bonding, the ring oscillator is activated by the signal EnableRO 150. When the signals Z1 160 and Z2 170 are set to be zero, the inverters 180 and 190 operate as normal inverters. When the Z1 (Z2) signal is set to be 1, the inverter 180 (190) can be converted to a Schmitt-Trigger inverter. The post-bond testing comprises measuring oscillation periods under three configurations: (1) Post-Config1: Z1Z2=00, (2) Post-Config2: Z1Z2=10 and (3) Post-Config3: Z1Z2=01.
TSVs can be characterized by analyzing the measured oscillation periods under the two (three) configurations for pre-bond (post-bond) testing. This is because the oscillation period of a ring oscillator depends on the TSV-based propagation delay. FIG. 2 illustrates an example of the relationship between the propagation delay of one TSV in the post-bond measurement setting (FIG. 1B) and ΔPeriod (=period of Post-Config2−period of Post-Config1) when no process variation exists. In the figure, the horizontal axis represents the propagation delay and the vertical axis represents ΔPeriod, both in the unit of nanosecond. By measuring the oscillation periods, not only the fault type of a parametric fault such as the resistive open fault and the leakage fault can be identified, but the fault effects in terms of propagation delay, voltage swing, or leakage current can be accessed. Powerful as the ring oscillator-based scheme is, there are challenges in implementing it. As a die may have at least hundreds of TSVs, test time, silicon area and routing are important factors that may determine whether a test architecture for the ring oscillator-based scheme is feasible or not.